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Languguage OS II Version 10-94 (Knowledge Media)(1994).ISO
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mcu332
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332equ.arc
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332RAM.EQU
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1990-03-12
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7KB
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128 lines
****************************************************************************
* $RCSfile: 332ram.equ $
* $Revision: 1.1 $
* $Date: 90/03/12 13:45:26 $
*
* -------------------------------------------------------------
* Module Name: 332RAM - MC68332 RAM Registers
* -------------------------------------------------------------
*
* Description:
* 1. This file contains EQUates for all the Standby RAM
* Module (RAM) registers and bits for the MC68332. Consult
* the "MC68332 System Integration Module User's Manual", part
* number SIM32UM/AD, for more details.
* 2. A 64-byte address space is reserved for the RAM, though not
* all are used.
* 3. The ABSOLUTE address area where the register array block
* appears in memory is specified by the value of REG$, which
* should be defined in the user's system definitions. The
* value of REG$ is $YFF000, where Y = M111 and M reflects the
* modmap bit (MM) in the module configuration register (MCR).
*
* REG$ value Comments
* ---------- ---------------------------------
* $007FF000 MCR MM bit = 0
* $00FFF000 MCR MM bit = 1 (reset default)
* $FFFFF000 MCR MM bit = 1 (reset default)
* Forces short addressing (unused
* upper address lines are ignored)
* 4. The following pages summarize these registers and their
* associated addresses.
*
* Notes:
* 1. Motorola reserves the right to make changes to this file.
* Although this file has been carefully reviewed and is
* believed to be reliable, Motorola does not assume any
* liability arising out of its use. This code may be freely
* used and/or modified at no cost or obligation to the user.
* 2. All descriptions are WORD values unless stated otherwise.
* 3. The DEF macro along with the BIT$CODE symbol controls the
* actual bit definitions. See the DEF macro in the DEF.MAC
* file for details.
* 4. This file was made for use with the Motorola Development
* Systems M68000 Family Structured Assembler for MS-DOS,
* known as M68MASM.
* 5. To use this file, either use an INCLUDE statement or just
* merge this file into your source code file. Consult your
* assembler's user's manual for the details specific to your
* situation. Reference the code segment example below for
* usage ideas (shown in M68MASM for MS-DOS syntax).
*
* REG$ EQU $FFFFF000 Register base address
* * NOTE: A31-24 unused in MC68332, so we set them all =1
* * in order to use absolute short addressing mode!
* NOLIST
* INCLUDE "DEF.MAC"
* INCLUDE "332RAM.EQU"
* LIST
* START CLR RAM$+RAMTST Absolute addressing!
* LEA RAM$,A6 . OR
* CLR (RAMTST,A6) Indexed addressing!
* * Bit number usage w/indexing!
* BCLR.B #.RAMDS,(RAMBAR+1,A6)
* OR.W (1<<.STOP)+(1<<.RASP),(RAMMCR,A6)
* * . OR
* * Bit value usage w/indexing!
* AND.W #(-_RAMDS-1)&$FFFF,(RAMBAR,A6)
* OR.W _STOP+_RASP,(RAMMCR,A6)
* * Bit field usage w/indexing!
* MOVE.B #(20*SDTEST_),(RAMTST,A6)
* * Bit field mask usage w/indexing!
* MOVE.W (RAMTST,A6),D0
* MOVE.W D0,D1
* AND.W #SDTEST_MSK,D0 Isolate SDTEST field
* MOVE.L #.SDTEST,D2
* LSR.W D2,d0 and right justify it!
* AND.W #SDTEST_NMSK,D1 Clear SDTEST field.
*
* For bit fields, a value (0-N) will be placed inside. As
* can be seen in the last line above, this is accomplished
* by multiplying the bit field label by the desired value
* for the field. This line initializes the RAMTST register
* which has one bit field, SDTEST. This field is initial-
* ized to 20 by this line (places a value of $2800 into the
* RAMTST register).
* 6. Be careful when using any of the BIT instructions (BCHG,
* BCLR, BSET, BTST), as they will only operate on a BYTE of
* memory, not a WORD. Thus to access a bit in the least
* significant half of a word sized register (B0-B7), "+1"
* must be added to the operand address. See the code
* segment example in item 5 above.
* 7. Because the equate files can generate many listing pages,
* the user may wish to disable the listing via NOLIST and
* LIST directives as seen in the above example code.
* 8. The latest version of this file is maintained on the
* Motorola FREEWARE Bulletin Board, 512/891-FREE (512/891-
* 3733). It operates continuously (except for maintenance)
* at 1200-2400 baud, 8-bits, no parity. Download the
* archive file 332EQU.ARC to get all the files.
*
****************************************************************************
*********************************************************************
* Define Module Base Address
*********************************************************************
RAM$ EQU REG$+$B00 RAM base address
*********************************************************************
* Define Registers and Bits
*********************************************************************
RAMMCR EQU $000 RAM Module Configuration Register
DEF STOP,B15 . stop control
DEF RASP,B8 . RAM array space
*-------------------------------------------------------------------*
RAMTST EQU $002 RAM Test Register
DEF SDTEST,B9,7 . soft detect test function (7 bits)
DEF RTBA,B8 . base address register R/W
*-------------------------------------------------------------------*
RAMBAR EQU $004 RAM Array Base Address/Status Register
* NOTE: RAMBAR is a WRITE-ONCE register!
DEF RAMBAS,B3,13 . RAM array base addr, A23-A11 (13 bits)
DEF RAMDS,B0 . RAM array disable
*-------------------------------------------------------------------*
*UNUSED EQU $006-$03F Unused positions
*********************************************************************